 # Project Setup Variables
  set PROJ_NAME "myproj"
  set PART "xc6slx45tfgg484-3"
  set BOARD "sp605"

  # Create the project - Builds project in the current directory.
  create_project $PROJ_NAME ./$PROJ_NAME -part $PART -force
  set_property board $BOARD [current_project]

# Create synthesis/implementation/simulation fileset
add_files -fileset sources_1 -norecurse {../../par/xilinx_ise/define.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/top/mac_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/tx/tx_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/tx/gmii2rgmii.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/rx/rx_top.v}
add_files -fileset sources_1 -norecurse {../../src/rtl/rx/rgmii2gmii.v}

# Create simulation only fileset
set_property SOURCE_SET sources_1 [get_filesets sim_1]

add_files -fileset sim_1 -norecurse {../../sim/top/testbench/top_bench.v}
add_files -fileset sim_1 -norecurse {../../sim/top/bfm/phy_rgmii_bfm.v}
add_files -fileset sim_1 -norecurse {../../sim/top/phy_rgmii_rx_source.pcap}

# Set individual file properties
set_property is_global_include true [get_files  ../../par/xilinx_ise/define.v]

set_property used_in_synthesis false [get_files  ../../sim/top/testbench/top_bench.v]
set_property used_in_synthesis false [get_files  ../../sim/top/bfm/phy_rgmii_bfm.v]
set_property used_in_implementation false [get_files  ../../sim/top/testbench/top_bench.v]
set_property used_in_implementation false [get_files  ../../sim/top/bfm/phy_rgmii_bfm.v]

#set_property file_type {Data Files} [get_files  ../../sim/top/phy_rgmii_rx_source.pcap]
#set_property used_in_synthesis false [get_files  ../../sim/top/phy_rgmii_rx_source.pcap]

# Update compile order
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

#reset_run synth_1
#reset_run impl_1

#launch_runs synth_1 -jobs 1
#wait_on_run synth_1

#launch_runs impl_1 -jobs 1
#wait_on_run impl_1

#launch_runs impl_1 -to_step write_bitstream
#wait_on_run impl_1

